The invention relates to an integrated circuit and to a method for testing the integrated circuit via contact areas disposed on a main area of the circuit.
Integrated circuits are fabricated on wafers composed of semiconductor material. Each wafer has a number, the number being very large under certain circumstances, of mutually adjacent integrated circuits which are disposed in such a way that the area of the wafer is utilized to the best possible effect. The main areas of the integrated circuits are usually rectangular. Contact areas are situated on the surface of each integrated circuit, via which contact area signals can be transferred from and to the integrated circuit. The contact areas are also referred to as pads.
In order to test the integrated circuits situated on the wafer, the contact areas are usually contact-connected to test probes (that is to say test contacts in the form of needles) of a test apparatus. The signals are then transferred from the test apparatus to the integrated circuit, and vice versa, via the test probes and the contact areas which are contact-connected thereto.
Many integrated circuits have contact areas only along two opposite sides of the main area. If two of the integrated circuits are disposed next to one another on a wafer, all of their contact areas can be contact-connected simultaneously to test probes without difficulty. However, there are also integrated circuits that have contact areas on more than two sides of their main area. In order to be able to test such a circuit, it is necessary for test probes to be contact-connected to the corresponding contact areas from all four sides. If two circuits of this type are adjacent to one another on the wafer, the contact areas cannot readily be contact-connected simultaneously to test probes since it is then possible for the test probes to experience a crossover, above all at the mutually adjacent sides of the two circuits. Therefore, adjacent circuits with contact areas on four sides are, as a rule, contact-connected and tested one after the other. This prolongs the time required for testing a plurality of adjacent circuits in comparison with the case of simultaneously testing the circuits.
It is accordingly an object of the invention to provide an integrated circuit and method for testing it that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which testing via its contact areas using test contacts is facilitated.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit, including: a first sub-circuit; a first contact area transferring data to and from the first sub-circuit during a first operating mode; and a second sub-circuit; a second contact area transferring data to and from the second sub-circuit in the first operating mode, in a second operating mode the second contact area transferring data to and from the first sub-circuit.
The integrated circuit according to the invention has at least one first and one second contact area for data transfer from and/or to a first and/or a second sub-circuit in a first operating mode of the circuit. It being the case that in a second operating mode of the circuit, the second contact area serves for data transfer from and/or to the first sub-circuit.
In the second operating mode, then, the second contact areas serve to transfer signals that are to be transferred via the corresponding first contact areas in the first operating mode. Therefore, the function performed by the first contact area in the first operating mode is taken over by the second contact area in the second operating mode. The corresponding signals are therefore fed into and/or removed from the circuit in the second operating mode at a different location (namely that of the second contact area) from that in the first operating mode. As a result, these signals can be transferred without any problems in the second operating mode if the first contact area can be contact-connected only with difficulty to test contacts of a test apparatus and the second contact area, on the other hand, can readily be contact-connected.
The circuit according to the invention is suitable for a procedure in which only the second contact areas, but not the first contact areas, are contact-connected to test probes in the second operating mode, with the result that the functions performed by the first contact areas in the first operating mode can then be tested via the second contact areas. This facilitates, in particular, the simultaneous testing of circuits which are adjacent on a wafer and in which the first contact areas are disposed on mutually facing sides of the circuits, where they can be contact-connected simultaneously to test contacts only with difficulty.
In the second operating mode, the second contact area may serve, on the one hand, exclusively to transfer signals that are transferred via the first contact areas in the first operating mode. The signals that are to be transferred via the second contact area in the first operating mode are not transferred via the second contact area in that case. This is possible, for example, if the second operating mode is a test operating mode of the circuit in which a smaller number of contact areas are required than in the first operating mode, because only specific functions of the circuit are tested.
In the second operating mode, the second contact area may also serve, in addition to transferring the signals which are to be transmitted via the first contact area in the first operating mode, furthermore to transfer the signals which it also transfers in the first operating mode. This can be realized for example by the second contact area serving to transfer the various types of signals using time division multiplexing in the second operating mode.
According to a development of the invention, the first and the corresponding second contact areas are disposed in respectively different rows of contact areas, the rows being respectively disposed parallel on different sides of a main area of the circuit.
In this case, in the second operating mode, bottlenecks in the event of contact-connecting the circuit to test probes at the side with the first contact areas are circumvented by displacing their function to the second contact areas. If there are two directly adjacent circuits on a wafer, e.g. the mutually facing sides constitute bottlenecks of this type, since it is there that, without the invention, test probes must be contact-connected on both circuits in direct proximity to one another, with the result that the risk of the test contacts experiencing a crossover is particularly high in this region. The invention makes it possible to gain space at the most critical location for attaching the test contacts (the location being the one at which the two circuits face one another) by the use of fewer test contacts than there are contact areas, it being possible for contact to be made with the remaining contact areas more easily as a result.
If the first contact areas are disposed on at least one of two opposite sides of the main area and the second contact areas are disposed on at least one of two other, likewise opposite sides, contact-connection bottlenecks at the first-mentioned two sides are circumvented in the second operating mode. Therefore, the simultaneous contact-connection and testing of at least three adjacent circuits is advantageously facilitated, which circuits are disposed in such a way that the first contact areas are in each case disposed on the side facing the adjacent circuit. At these sides, fewer contact areas than are present have to be contact-connected in the second operating mode. On the other hand, those sides on which the second contact areas are situated can be contact-connected without difficulty and without the test probes experiencing a crossover, since no adjacent circuits which are to be contact-connected simultaneously are disposed on these sides. Of course, it is also possible for more than three of the circuits according to the invention to be adjacent to one another with regard to their sides having the first contact areas and to be tested simultaneously.
According to a development, the integrated circuit is an integrated memory circuit in which at least one of the first contact areas is an address contact area which serves, in the first operating mode, to transfer an address signal for addressing the memory circuit, and in which the corresponding second contact area serves, in the second operating mode, to transfer the address signal. The address signal serves for addressing memory cells of the memory circuit.
Especially for dynamic memories (DRAMs), there is a JEDEC standard which provides for the initiation of test operating modes (Test Mode Entry) using all the address terminals. If it is desired that the functions provided there will be fulfilled both in the first and in the second operating mode, the function of all the address contact areas must therefore also be available in the second operating mode. This can be achieved by the invention by the function of the first contact area being displaced to the second contact area in the second operating mode in the manner described. In the case of this memory circuit, therefore, a JEDEC Test Mode Entry and complete addressability of its memory cells are also ensured in the second operating mode, if the second contact areas are contact-connected instead of the first contact areas.
It is expedient when the second contact area is a data contact area that serves, in the first operating mode, to transfer data which are stored and/or are to be stored in the circuit. This development is suitable e.g. for a memory circuit whose second operating mode is a test operating mode requiring all the external address signals which are required in the first operating mode as well, but not all the data contact areas which are used in the first operating mode.
The function of the second contact area as a data contact area is dispensable in the second operating mode for example when the transfer of the corresponding data is obviated by a self-test carried out (under certain circumstances only partly) on the circuit. In one kind of self-test, e.g. required test data are generated on the memory circuit, written to the memory cells, read back from the cells and compared with the written-in desired values within the memory circuit. In the extreme case, just a single result signal is communicated to a point outside the circuit via one of the contact areas after the conclusion of the self-test, which result signal indicates whether or not the test has been passed (pass/fail signal). If one data contact area is used for this purpose, all the further data contact areas that are consequently not required are available in the test operating mode as potential second contact areas in the sense of the invention. These contact areas may be provided for the replacement of corresponding first contact areas.
The test data can, for example, also be read from and/or written to the memory circuit in another compressed form in the second operating mode, the memory cell contents read out are partly evaluated on the memory circuit and only the result of the evaluation are communicated externally via the contact areas. This, too, can be realized using a relatively small number of data terminals, with the result that, in the second operating mode, not all of the data contact areas are required and, therefore, they can likewise be provided as second contact areas.
According to a development, the integrated circuit has a third contact area for the application of a control signal, the circuit being transferred from the first operating mode to the second operating mode as a function of the control signal. The control signal enables the function of the first contact areas to be displaced to the second contact areas. The displacement being controlled externally via the third contact area, with the result that the operation in the second operating mode can subsequently be begun without the first contact areas being contact-connected.
Since the second operating mode serves to facilitate the contact-connection of the circuit to test contacts of a test apparatus, the second operating mode is no longer necessary once the integrated circuit is removed from the congested wafer. In particular, it may be provided that in the case of a housed IC, the third contact area is not connected to a housing terminal (Pin) present exclusively for this. The area is then used merely as a test contact area during the test phase of the unhoused IC, the test phase following the fabrication of the circuit, and an additional housing terminal is not necessary. Conventional housings can be used instead.
The test method according to the invention can be applied, in particular, to the integrated circuit according to the invention. It provides the following steps in the second operating mode:
a) the second contact areas are contact-connected to test contacts of a test apparatus, and
b) signals which are transferred via the corresponding first contact areas in the first operating mode of the circuit are transferred via the second contact areas.
In the second operating mode, it is advantageous that the first contact areas do not have to be contact-connected to test contacts, since their function is taken over by the second contact areas. The position of the second contact area can then be chosen such that contact can be made with it more simply than with the first contact area. This is particularly advantageous when testing adjacent integrated circuits on a wafer, the first contact areas of which circuits are disposed in such a way that their simultaneous contact-connection to test contacts is possible only with a great deal of difficulty. The test method according to the invention facilitates the simultaneous testing of adjacent circuits of this type. As a result, adjacent circuits do not have to be tested one after the other, the time required for testing all the circuits thereby being reduced.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit and method for testing it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.